fpga/flash/testbench.cpp

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2026-01-26 18:10:18 +01:00
// testbench.cpp
#include <stdlib.h>
#include <iostream>
#include <verilated_vcd_c.h>
#include <verilated.h>
#include "Vtop.h"
#define MAX_SIM 100000
int main(int argc, char** argv) {
// Initialize Verilator
// Instantiate the design
Vtop* dut = new Vtop;
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC;
dut->trace(m_trace, 5);
m_trace->open("waveform.vcd");
// Initialize inputs
dut->sysclk = 0;
dut->sys_rst_n = 1;
// Simulation loop
for (int cycle = 0; cycle < MAX_SIM; cycle++) {
dut->sysclk ^= 1;
dut->miso ^= 1;
dut->eval();
m_trace->dump(cycle);
// Read and display outputs
// printf("Cycle %3d: led = %3d\n", cycle, dut->counter);
}
// Cleanup
m_trace->close();
delete dut;
return 0;
}